In recent years, portable communication terminal devices that have been widespread explosively have been required to be faster, and PLL circuits operated in a wide frequency bandwidth have been essential as the frequency synthesizer of a radio section. In the PLL circuits, a circuit that frequency-divides a high frequency signal to a low frequency is a frequency divider, and in particular, an injection locked frequency divider in a frequency bandwidth of at least 10 GHz has been known (for instance, see Non-Patent Literature 1).
FIG. 1 is a circuit diagram showing the configuration of injection locked frequency divider 10 described in Non-Patent Literature 1.
As shown in FIG. 1, injection locked frequency divider 10 includes ring oscillator 40 that cascade-connects first amplifier circuit 41, second amplifier circuit 42, and third amplifier circuit 43 in three stages in a ring (also called a loop) and signal injection circuit 50 that outputs injection signal I1.
First amplifier circuit 41 includes N-channel MOS (Metal Oxide Semiconductor) transistor 11 and P-channel MOS transistor 12. The gate of N-channel MOS (Metal Oxide Semiconductor) transistor 11 receives the feedback output of third amplifier circuit 43. P-channel MOS transistor 12 functions as a load.
Second amplifier circuit 42 includes N-channel MOS transistor 21 and P-channel MOS transistor 22. The gate of N-channel MOS transistor 21 receives the output of first amplifier circuit 41. P-channel MOS transistor 22 functions as a load.
Third amplifier circuit 43 includes N-channel MOS transistor 31 and P-channel MOS transistor 32. The output of second amplifier circuit 42 is inputted to the gate of N-channel MOS transistor 31. P-channel MOS transistor 32 functions as a load.
Signal injection circuit 50 is connected to the gates of P-channel MOS transistors 12, 22, and 32 in all stages.
The sources of P-channel MOS transistors 12, 22, and 32 are connected to high potential power source Vdd, and the sources of N-channel MOS transistors 11, 21, and 31 are grounded.
The operation of injection locked frequency divider 10 will be described.
FIG. 2 is a diagram showing the frequencies of the output signal of injection locked frequency divider 10, and FIG. 3 is a diagram showing the phases in the respective stages of ring oscillator 40.
As shown in FIG. 2, when the injection signal from signal injection circuit 50 is not inputted, oscillation signal F1 of free-running frequency f0, second-order harmonic component F2 of frequency 2fo, and third-order harmonic component F3 of frequency 3fo occur in the output of ring oscillator 40.
Next, when injection signal I1 from signal injection circuit 50 is the signal near frequency 3fo, injection signal T1 and second-order harmonic component F2 are mixed so that output signal I2 provided by down-converting the injection signal occurs near free-running frequency fo. Oscillation signal F1 of ring oscillator 40 is drawn to and synchronized with the frequency of output signal I2.
The phases of oscillation signal F1 in the respective stages of ring oscillator 40 at this time have a phase rotation of 120°, as shown in FIG. 3. Therefore, when the first stage has a phase rotation of 0′, the second stage has a phase rotation of ±120° and the third stage has a phase rotation of ±240°. In addition, since the phases of third-order harmonic component F3 in the respective stages become three times those of oscillation signal F1, all the stages have a phase rotation of 0° and are in phase. That is, it suffices that the phases of injection signal I1 in the respective stages are all in phase.
In this way, since the input of injection signal I1 near frequency 3fo provides output signal I2 near free-running frequency fo, injection locked frequency divider 10 is operated as a frequency divider for ⅓ frequency division.
FIG. 4 is a diagram showing the frequency characteristic of the voltage amplitude of injection signal I1. Injection signal I1 is the signal inputted from signal injection circuit 50 necessary for stable synchronization of injection locked frequency divider 10.
As shown in FIG. 4, it suffices that the voltage amplitude of the injection signal is minimum near the frequency three times free-running frequency fo of ring oscillator 40, and injection locked frequency divider 10 can be operated in a frequency bandwidth of about 5 GHz at a voltage amplitude of 200 mVpp.